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CY23020-1
20-output, 200-MHz Zero Delay Buffer
Features
* * * * * * * 335 ps max Total Timing BudgetTM (TTB)TM window 2.5V or 3.3V outputs 20 LVCMOS outputs 50 MHz to 200 MHz output frequency 50 MHz to 200 MHz input frequency Integrated phase-locked loop (PLL) with lock indicator Spread AwareTM--designed to work with SSFTG reference signals * 3.3V core power supply * Available in 48-pin TSSOP and QFN packages
Description
The CY23020-1-1 is a high-performance 200-MHz PLL-based zero delay buffer designed for high-speed clock distribution applications. The device features a guaranteed TTB window specifying all occurrences of output clocks with respect to the input reference clock across variations in output frequency, supply voltage, operating temperature, input edge rate, and process. The CY23020-1 outputs are three-state when S1 = S2 = 0 for reduced power. When S1 = 1 and S2 = 0 the PLL is bypassed and the CY23020-1 functions as a fan-out buffer.
Block Diagram
LOCKED
Pin Configurations
LOCK 1 2 3 4 5 6 7 8 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 9 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDDC GNDC REF- REF+ VDD Q19 Q18 GND Q17 Q16 VDD Q15 Q14 GND Q13 Q12 VDD Q11 Q10 GND GNDC VDDC C1 GND
FBOUT REF PLL FBIN Div Q1 Q2
NC FBIN- FBIN+ VDD FBOUT Q1 GND
C1
C1C1
C1 S1:2 RANGE MUL
Output Control Logic
Q3
Q17 Q18 Q19
VDD Q4 Q5 GND Q6 Q7 VDD Q8 Q9
48 F B O U T +
47 V D D
46 F B I N +
45 F B I N -
44 N C
1 2 3 4 5 6
Q1 VSS Q2 Q3 VDD Q4 Q5 VSS
43 L O C K
42 V D D C
41 V S S C
40 R E F -
39 R E F +
38 V D D
37 Q 1 9 Q 18 36 VSS 35 Q 17 34 Q 16 33
GND S2 S1 MUL RANGE
48-pin TSSOP
4 8 -p in Q F N
VDD 32 Q 15 31 Q 14 30 VSS 29
7 8 9 10 11 12
Q6 Q7 VDD Q8 V S S C Q 1 0
Q 13 28 Q 12 27 VDD 26 Q 11 25
Q 9
V S S
S 2
S 1
M U L
R A N G E 18
G N D
C 1
V D D C
V S S
13
14
15
16
17
19
20
21
22
23
24
Cypress Semiconductor Corporation Document #: 38-07120 Rev. *B
*
3901 North First Street
*
San Jose
*
CA 95134 * 408-943-2600 Revised November 5, 2002
CY23020-1
Q2
CY23020-1
Pin Definitions[2]
Pin No. Pin Name REF+ REF- TSSOP 45 46 QFN 39 40 Pin Type I Pin Description Reference Inputs: Output signals are synchronized to the crossing point of REF+ and REF- signals. Therefore REF- must be tied to VREF as defined in the DC characteristics table. In DC mode, the REF+/REF- inputs must be held at opposite logical states. For optimal performance, the impedances seen by these two inputs must be equal. Feedback Inputs: Input FBIN+ must be fed by one of the outputs to ensure proper functionality. If the trace between FBIN+ and FBOUT is equal in length to the traces between the outputs and the signal destinations, then the signals received at the destinations will be synchronized to the clock signal at REF+ input. FBIN- must be tied to VREF as defined in the DC characteristics table. In DC mode, FBIN+/FBIN- inputs must be held at opposite logical states. For best performance, the impedances seen by these two inputs must be equal. Feedback Output: In order to complete the phase locked loop, an output must be connected back to the FBIN+ pin. Any of the outputs may actually be used as the feedback source. Outputs: Refer to Tables 1-4 for the configuration of these outputs.
FBIN+ FBIN-
4 3
46 45
I
FBOUT
6
48
O
Q1:19
7, 9, 10, 12, 13, 15, 16, 18, 19, 30, 31, 33, 34, 36, 37, 39, 40, 42, 43 24 1
1,3,4,6,7,9,1 0,12,13,24,2 5,27,28,30,3 1,33,34,36,3 7 18 43
O
RANGE1 LOCK
I O
Frequency Range Selection Input: To determine the correct connection for this pin, refer to Table 2. This should be a static input PLL Locked Output: When this output is HIGH, the PLL in the CY23020-1 is in steady state operation mode (Locked). When this signal is LOW, the PLL is in the process of locking onto the reference signal. Output/PLL Enable Selection bits: To determine appropriate settings, refer to Table 1. Power Connection Analog Power Connection: Connect to 3.3V. Analog Ground Connection: Connect to common system ground plane. Output Buffer Power Connections: Connect to 2.5 or 3.3V, whichever is to be the reference for the output signals. Ground Connections: Connect to common system ground plane. Ground Connections Ground Connections Multiplication Factor Select: When set HIGH, the outputs will run at twice the speed of the reference signal. This should be a static input Output Configuration Bit: Establishes either 2.5V or 3.3V Full Swing Operation. To determine appropriate setting, refer to Table 3. This should be a static input Do Not Connect: This pin must be left floating. This pin is used by the factory for testing purposes.
S1:2 VDD VDDC GNDC VDD GND VSS VSSC MUL[1] C1[1]
22, 21
16,15 5,11,26, 32
I P P G P G G G I I
27, 48 28, 47 5, 11, 17, 32, 38, 44 8, 14, 20, 25, 29, 35, 41
21, 42 38,47 19 2,8,14,23,29 ,35 22,41
23 26
17 20
NC
2
44
NC
Note: 1. RANGE and MUL have a ~100k pull-down. C1 has a 50k pull-down. These inputs (RANGE, MUL, C1) are static. 2. There are no power-up sequence requirements on the power supply pins of the CY23020-1.
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CY23020-1
Table 1. Output Configuration S1 0 0 1 1 S2 0 1 0 1 Qx source Three-state Reserved Reference input PLL output Shutdown Active PLL Shutdown adjusted, in phase, to occur later or more often before the device's input clock to compensate for a design's physical delay inadequacies. Most commonly this is done using a simple PCB trace as a time delay element. The longer the trace the earlier the output clock edges occur with respect to the reference input clock edges. In this way such effects as undesired transit time of a clock signal across a PCB can be compensated for.
Inserting Other Devices in Feedback Path
Due to the fact that the device has an external feedback path the user has a wide range of control over its output to input skewing effect. One of these is to be able to synchronize the outputs of an external clock that is resultant from any of the output clocks. This implementation can be applied to any device (ASIC, multiple output clock buffer/driver, etc.) which is put into the feedback path. Referring to Figure 1, if the traces between the ASIC/buffer and the destination of the clock signal(s) (A) are equal in length to the trace between the buffer and the FBIN pin (B), the signals at the destination device(s) (C) will be driven high at the same time the Reference clock provided to the ZDB goes high. Synchronizing the other outputs of the ZDB to the outputs from the ASIC/Buffer is more complex however, as any propagation delay in the ASIC/Buffer must be accounted for. There are constraints when inserting other devices. If the devices contain Phase-Locked Loops (PLLs) or excessively long delay times they can easily cause the overall clocking system to become unstable as the components interact. For these designs it is advisable to contact Cypress for applications support.
Reference Signal Feedback Input Zero Delay Buffer
Table 2. Frequency Range Setting Range 0 1 Output Frequency Range 50-100 MHz 100-200 MHz
Table 3. Output Configuration Setting C1 0 1 3.3V Full swing 2.5V Full swing Output Type
Table 4. Frequency Multiplication Table MUL 0 1 Output Frequency FOUT = FREF FOUT = FREF x 2
Spread Aware
Many systems are designed to utilize Spread Spectrum Modulation clock technology. This technology is used to dramatically reduce Electro Magnetic Interference (EMI) in digital systems. Cypress has pioneered SSFTG development, and this product is designed to pass any SSFTG modulation that is present on the REF+ pin to its output clock signals. This capability also enhances the part to produce clocks with significantly smaller jitter and tracking skew on its output clocks. This is especially beneficial in systems that have downstream PLLs present. For more details on Spread Spectrum timing technology, please see the Cypress application note titled, "EMI Suppression Techniques with Spread Spectrum Frequency Timing Generator (SSFTG) ICs."
ASIC/ Buffer
C
A
B
Figure 1. Output Buffer in the Feedback Path
Component Characterization Set-up
24 O hm
o n c h ip o u tp u t b u ffe r
How to Implement Zero Delay
Typically, zero delay buffers (ZDBs) multiply (fan-out) single clock signals quantity while simultaneously reducing or mitigating the time delay associated with passing the clock through a buffering device. In many cases the output clock is
4 in c h 5 0 o h m T lin e 5 pf
Figure 2. Termination Networks
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CY23020-1
Cbyp 50 FBINFBIN+ RefRef+ Vref Source 50 Cbyp
RS FBOUT Q1 CL Q2 . . . Q19 Q18 Q17 . . .
RS CL
Q9
Q10
Figure 3. Establishing Reference Voltages The CY23020-1 uses a differential input receiver to increase it's rejection of common mode input noise and thus increase device performance. To ensure that any noise appears equally on both the REF- and REF+ pins, it is necessary to match the external impedance and circuitry seen at these pins. Figure 3 shows how this may be accomplished. The reference voltage, VREF can be generated by a resistor divider from a power supply. This potential will adjust the FBIN+ input's triggering threshold. The reference voltage should be well bypassed so as to not introduce any single ended noise to the device. Note that the impedance (50 ohms) is also matched to the FBIN+ line. The 50 ohm resistor is used to create a "like" load on the REF- input clock signal and matches the 50-ohm source impedance of the REF+ input signal. If the input impedance is significantly different than 50 ohms, the reference resistor should be adjusted accordingly.
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CY23020-1
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other condiParameter VDD VIN TSTG TA TJ PD Description Voltage on any VDD pin with respect to GND Voltage on any input pin with respect to GND Storage Temperature Operation Temperature (TSSOP) Operation Temperature (QFN) Junction Temperature Package Power Dissipation (TSSOP) tions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Test Conditions -0.5 to +5.0 -0.5 to VDD + 0.5 -65 to +150 0 to +70 -40 to +85 +150 max 1 Unit V V C C C C W
Full Swing DC Electrical Characteristics VDDC = 3.3V 5%, VDD = 2.5V 5% or 3.3V 5%
Parameter VIH VIL VIH VIL IIH IIL IPD CIN Description REF+, FBIN+ Inputs only REF+, FBIN+ Inputs only Logic Inputs only Logic Inputs only Output Current in HIGH state VIN = VDD, (MUL, C1, and RANGE) VIN = VDD, (REF, FBINx, S1, S2) Output Current in LOW state VIN = 0V Power-down Current Input Capacitance PLL disable mode, S1:S2 = 0 5 0.7 x VDDC 0.3 x VDDC 100 10 10 100 A pF Test Conditions Min. 2.0 0.8 Typ. Max. Unit V V V V A
2.5V Full Swing DC Electrical Characteristics VDDC = 3.3V 5%, VDD = 2.5V 5%
Parameter IDD IOH IOL VREF Description Supply Current Test Conditions Unloaded, 200 MHz 14 1.19 1.50 Min. Typ. Max. Unit 225 -14 mA mA mA V
Output Current in HIGH State Measured at pin, no load network, VOH = VDD - 0.35V Output Current in LOW State Measured at pin, no load network, VOL = 0.35V External Reference Voltage Single-ended inputs, see Figure 3
3.3V Full Swing DC Electrical Characteristics VDDC = 3.3V 5%, VDD = 3.3V 5%
Parameter IDD IOH IOL VREF Description Supply Current Output Current in LOW State External Reference Voltage Test Conditions Unloaded, 200 MHz measured at pin, no load network, VOL = 0.4V Single-ended inputs, see Figure 3 14 0.34 x VDD 0.46 x VDD Min. Typ. Max. 240 -18 Unit mA mA mA V
Output Current in HIGH State measured at pin, no load network, VOH = 2.4V
Document #: 38-07120 Rev. *B
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CY23020-1
Full Swing AC Electrical Characteristics VDDC = 3.3V 5%, VDD = 2.5V 5% or VDD = 3.3V 5%, Load: (See term. diagram, CL= 5 pF) TSSOP Package
Parameter FIN FOUT tISR tR tF tIDC tD tPD tPD2 tSK tTB tJC tJC_RMS tJP tJP_RMS tJL tJLRMS tJC2 tJCRMS2 tJP2 tJPRMS2 tJL2 tJLRMS2 PSRR (Core) PSRR (Output) tLOCK tPWD tTSK Description Input Frequency Output Frequency Input Slew Rate (+ or -) Output Rise Rate Output Fall Rate Input Duty Cycle Output Duty Cycle REF-FBIN skew REF-FBIN skew Output-Output Skew Total Timing Budget window
[3, 4]
Test Conditions
Min. 50 50
Typ.
Max. Unit 200 MHz 200 6.5 6.5 6.5 60 55 57 175 225 175 225 85 335 385 95 15 95 15 150 30 145 25 150 40 150 30 MHz V/ns V/ns V/ns % % ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps pspp /V pspp /V 1 1 100 ms ms ps
Measured between 20% and 80% of input swing Measured between 20% and 80% of output swing Measured between 80% and 20% of output swing Tested at 50% swing Measured at VDD/2, FOUT < 167 MHz Measured at VDD/2, FOUT >167 MHz Fout = Fref, VDD = 2.5V Fout = Fref, VDD = 3.3V Fout = Frefx2, VDD = 2.5V Fout = Frefx2, VDD = 3.3V Refin to any output, Fout = Fref Refin to any output, Fout = Fref x 2 All outputs active, Fout = Fref All outputs active, Fout = Fref All outputs active, Fout = Fref All outputs active, Fout = Fref All outputs active, Fout = Fref All outputs active, Fout = Fref All outputs active, Fout = Fref x 2 All outputs active, Fout = Fref x 2 All outputs active, Fout = Fref x 2 All outputs active, Fout = Fref x 2 All outputs active, Fout = Fref x 2 All outputs active, Fout = Fref x 2 1Vpp modulation of 10 kHz-10MHz 1Vpp modulation of 10 kHz-10MHz
1 1 1 40 45 43 -175 -175 -175 -225
Peak Cycle-Cycle Jitter (1000 cycles max) RMS Cycle-Cycle Jitter Period Jitter p-p RMS Period Jitter I/O Phase Jitter p-p RMS I/O Phase Jitter Peak Cycle-Cycle Jitter (1000 cycles max) RMS Cycle-Cycle Jitter Period Jitter p-p RMS Period Jitter I/O Phase Jitter p-p RMS I/O Phase Jitter I/O Phase Jitter Sensitivity to Power Supply Variations I/O Phase Jitter Sensitivity to Power Supply Variations Power-up lock time Power-down time Spread Spectrum Tracking skew
300 700
Notes: 3. MAX(TPD_MAX - TPD_MIN, TPD_MAX,(-1)*TPD_MIN) where TPD _MAX is the longest delay of refin to any output measured over at least 1000 cycles and TPD_MIN is the minimum (may be negative) delay observed over all outputs over at least 1000 cycles. 4. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect this parameter.
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CY23020-1
Full Swing AC Electrical Characteristics VDDC =3.3V 5%, VDD = 2.5V 5% or VDD = 3.3V 5%,
Load: (See term. diagram, CL= 5 pf) QFN Package Parameter FIN FOUT tISR tR tF tIDC tD tPD tPD2 tSK tTB tJC tJC_RMS tJP tJP_RMS tJL tJLRMS tJC2 tJCRMS2 tJP2 tJPRMS2 tJL2 tJLRMS2 PSRR (Core) PSRR (Output) tLOCK tPWD tTSK Description Input Frequency Output Frequency Input Slew Rate (+ or -) Output Rise Rate Output Fall Rate Input Duty Cycle Output Duty Cycle REF-FBIN skew REF-FBIN skew Output-Output Skew Total Timing Budget window[3,4] Refin to any output, Fout = Fref All outputs active, Fout = Fref x 2 Peak Cycle-Cycle Jitter (1000 cycles max) RMS Cycle-Cycle Jitter Period Jitter p-p RMS Period Jitter I/O Phase Jitter p-p RMS I/O Phase Jitter Peak Cycle-Cycle Jitter (1000 cycles max) RMS Cycle-Cycle Jitter Period Jitter p-p RMS Period Jitter I/O Phase Jitter p-p RMS I/O Phase Jitter I/O Phase Jitter Sensitivity to Power Supply Variations I/O Phase Jitter Sensitivity to Power Supply Variations Power-up lock time Power-down time Spread Spectrum Tracking skew All outputs active, Fout = Fref All outputs active, Fout = Fref All outputs active, Fout = Fref All outputs active, Fout = Fref All outputs active, Fout = Fref All outputs active, Fout = Fref All outputs active, Fout = Fref x 2 All outputs active, Fout = Fref x 2 All outputs active, Fout = Fref x 2 All outputs active, Fout = Fref x 2 All outputs active, Fout = Fref x 2 All outputs active, Fout = Fref x 2 1Vpp modulation of 10 kHz-10MHz 1Vpp modulation of 10 kHz-10MHz 300 700 1 1 100 Measured between 20% and 80% of input swing Measured between 20% and 80% of output swing Measured between 80% and 20% of output swing Tested at 50% swing Measured at VDD/2 Fout = Fref, VDD = 2.5V Fout = Fref, VDD = 3.3V Fout = Frefx2, VDD = 2.5V Fout = Frefx2, VDD = 3.3V Test Conditions Min. 50 50 1 1 1 40 45 -175 -100 -175 -150 Typ. Max. Unit 200 MHz 200 MHz 6.5 6.5 6.5 60 55 175 175 175 175 85 335 385 95 12 95 17 170 22 145 24 170 28 170 28 V/ns V/ns V/ns % % ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps pspp /V pspp /V ms ms ps
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CY23020-1
Ordering Information
Base Part # CY23020ZC-1 CY23020ZC-1T CY23020LFI-1 CY23020LFI-1T 48-pin TSSOP[5] Package 48-pin TSSOP--Tape and Reel 48- pin QFN 48-pin QFN--Tape and Reel Temperature Range Commercial, 0C to +70C Commercial, 0C to +70C Industrial, -40C to +85C Industrial, -40C to +85C
Package Diagrams
48-Lead Thin Shrunk Small Outline Package, Type II (6 mm x 12 mm) Z48
51-85059-B
Note: 5. Theta J = 95 C/W for TSSOP package.
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CY23020-1
Package Diagrams (continued)
48-Lead QFN (7x7 mm) LF48
51-85152-*A
Spread Aware, Total Timing Budget, and TTB are trademarks of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-07120 Rev. *B
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(c) Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY23020-1
Document Title: CY23020-1 20-output, 200-MHz Zero Delay Buffer Document Number: 38-07120 REV. ** *A *B ECN No. 109287 113758 118945 Issue Date 10/30/01 07/22/02 11/06/02 Orig. of Change SZV CTK HWT New Data Sheet Updated to reflect latest characteristics data Added the QFN Package in this device Description of Change
Document #: 38-07120 Rev. *B
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